Samsung Exynos 4412 芯片数据手册

Exynos 是韩国三星电子所发展的处理器代号。
Exynos源自希腊文字exypnos，意思是智慧。三星的Galaxy S II就是使用自家的Exynos 4210处理器。

2011年9月三星发布一款双核处理器Exynos 4212，采用ARM Cortex-A9架构，主频为1.5GHz。2011年12月三星发表全新Exynos 5250微处理器，32nm制程技术，运作时脉高达2GHz，未来主要将应用在平板装置。

Exynos SoC 列表

型号	半导体技术	CPU 指令集	CPU	GPU	内存技术	可达性	应用装置
Exynos 3 Single （内部编号：Exynos 3110 ；旧称：S5PC110 / Hummingbird）	45 nm	ARMv7	1 GHz单核ARM Cortex-A8	200 MhzPowerVRSGX540	LPDDR1, LPDDR2, or DDR2	2010	Samsung Galaxy S line、Samsung GT-S8500 Wave、Samsung Wave II S8530、Nexus S、魅族 M9、Samsung Galaxy Tab、Samsung Droid Charge、Exhibit 4G、Samsung Infuse
Exynos 4 Dual 45nm （内部编号：Exynos 4210 ）	45 nm	ARMv7	1.2-1.4 GHz双核ARM Cortex-A9	ARM Mali-400 MP4	LPDDR2, DDR2 or DDR3	2011	Samsung Galaxy S II、Samsung Galaxy Note、Samsung Galaxy Tab 7.7、Hardkernel ODROID-A、魅族 MX、Cotton Candy by FXI Tech
Exynos 4 Dual 32nm （内部编号：Exynos 4212 ）	32 nm	ARMv7	1.5 GHz双核ARM Cortex-A9	ARM Mali-400 MP4	LPDDR2, DDR2 or DDR3	2011	魅族MX 双核升级版
Exynos 4 Quad （内部编号：Exynos 4412 ）	32 nm	ARMv7	1.4-1.6 GHz四核ARM Cortex-A9	440 MHz ARMMali-400MP4	LPDDR2, DDR2 or DDR3	2012	Samsung Galaxy S III、魅族MX四核、魅族MX2[6]、Samsung Galaxy Note 10.1、Samsung Galaxy Note II（Mali-400 MP4 @ 533 MHz)、联想 K860、Samsung Galaxy Note 8
Exynos 5 Dua （内部编号：Exynos 5250 ）	32 nm	ARMv7	1.7-2.0 GHz双核ARM Cortex-A15 MPCore	ARM Mali-T604		2012	Chromebook、Nexus 10
Exynos 5 Octa （内部编号：Exynos 5410 ）	28 nm	ARMv7	1.6-1.8 GHz四核ARM Cortex-A15 MPCore+1.2 GHz四核ARM Cortex-A7 (ARM big.LITTLE)	PowerVR SGX 544MP3		2013	Samsung Galaxy S IV国际版
Exynos 5450	28 nm	ARMv7	1.7-2.0 GHz四核ARM Cortex-A15 MPCore	ARM Mali-T658[来源请求]		2013

文档目录

1 PRODUCT OVERVIEW ................................................................................. 1-1
1.1 Introduction ............................................................................................................................................. 1-1
1.2 Features .................................................................................................................................................. 1-2
1.2.1 Multi-Core Processing Unit ............................................................................................................... 1-4
1.2.2 Memory Subsystem .......................................................................................................................... 1-5
1.2.3 Multimedia ....................................................................................................................................... 1-6
1.2.4 Audio Subsystem .............................................................................................................................. 1-8
1.2.5 Image Signal Processing Subsystem ............................................................................................... 1-8
1.2.6 Connectivity ..................................................................................................................................... 1-9
1.2.7 System Peripheral .......................................................................................................................... 1-11
1.3 Conventions .......................................................................................................................................... 1-13
1.3.1 Register RW Conventions .............................................................................................................. 1-13
1.3.2 Register Value Conventions ........................................................................................................... 1-13
2 MEMORY MAP .............................................................................................. 2-1
2.1 Overview ................................................................................................................................................. 2-1
2.2 SFR Base Address ................................................................................................................................. 2-2
3 CHIP ID .......................................................................................................... 3-1
3.1 Overview ................................................................................................................................................. 3-1
3.2 Register Description ................................................................................................................................ 3-2
3.2.1 Register Map Summary .................................................................................................................... 3-2
4 GENERAL PURPOSE INPUT/OUTPUT (GPIO) CONTROL ......................... 4-1
4.1 Overview ................................................................................................................................................. 4-1
4.2 Features .................................................................................................................................................. 4-3
4.2.1 Input/Output Description ................................................................................................................... 4-3
4.3 Register Description ................................................................................................................................ 4-5
4.3.1 Registers Summary .......................................................................................................................... 4-5
4.3.2 Part 1 ............................................................................................................................................. 4-20
4.3.3 Part 2 ........................................................................................................................................... 4-124
4.3.4 Part 3 ........................................................................................................................................... 4-289
4.3.5 Part 4 ........................................................................................................................................... 4-298
5 CLOCK MANAGEMENT UNIT ...................................................................... 5-1
5.1 Overview ................................................................................................................................................. 5-1
5.2 Clock Domains ........................................................................................................................................ 5-1
5.3 Clock Declaration .................................................................................................................................... 5-3
5.3.1 Clocks from Clock Pads ................................................................................................................... 5-3
5.3.2 Clocks from CMU .............................................................................................................................. 5-4
5.4 Clock Relationship .................................................................................................................................. 5-5
5.4.1 Recommended PLL PMS Value for APLL and MPLL ...................................................................... 5-7
5.4.2 Recommended PLL PMS Value for EPLL ........................................................................................ 5-8
5.4.3 Recommended PLL PMS Value for VPLL ........................................................................................ 5-9
5.5 Clock Generation .................................................................................................................................. 5-10
5.6 Clock Configuration Procedure .............................................................................................................. 5-15
5.6.1 Clock Gating .................................................................................................................................. 5-16
5.6.2 Clock Diving ................................................................................................................................... 5-16
5.7 Special Clock Description ...................................................................................................................... 5-17
5.7.1 Special Clock Table ........................................................................................................................ 5-17
5.8 CLKOUT ................................................................................................................................................ 5-20
5.9 I/O Description ...................................................................................................................................... 5-23
5.10 Register Description ............................................................................................................................. 5-24
5.10.1 Register Map Summary ................................................................................................................ 5-26
6 INTERRUPT CONTROLLER ......................................................................... 6-1
6.1 Overview ................................................................................................................................................. 6-1
6.2 Features .................................................................................................................................................. 6-2
6.2.1 Security Extensions Support ............................................................................................................ 6-2
6.2.2 Implementation-Specific Configurable Features .............................................................................. 6-3
6.3 Interrupt Source ...................................................................................................................................... 6-4
6.3.1 Interrupt Sources Connection ........................................................................................................... 6-4
6.3.2 GIC Interrupt Table ........................................................................................................................... 6-5
6.4 Functional Overview .............................................................................................................................. 6-13
6.5 Register Description ............................................................................................................................... 6-14
6.5.1 Register Map Summary .................................................................................................................. 6-14
7 INTERRUPT COMBINER .............................................................................. 7-1
7.1 Overview ................................................................................................................................................. 7-1
7.2 Features .................................................................................................................................................. 7-1
7.3 Functional Description ............................................................................................................................. 7-2
7.3.1 Block Diagram ................................................................................................................................. 7-2
7.4 Interrupt Sources..................................................................................................................................... 7-3
7.4.1 Interrupt Combiner ............................................................................................................................ 7-3
7.5 Functional Description ............................................................................................................................. 7-8
7.6 Register Description ................................................................................................................................ 7-9
7.6.1 Register Map Summary .................................................................................................................... 7-9
7.6.2 Interrupt Combiner .......................................................................................................................... 7-10
8 DIRECT MEMORY ACCESS CONTROLLER (DMAC) ................................. 8-1
8.1 Overview ................................................................................................................................................. 8-1
8.2 Features .................................................................................................................................................. 8-2
8.3 Register Description ................................................................................................................................ 8-5
8.3.1 Register Map Summary .................................................................................................................... 8-5
8.4 Instruction .............................................................................................................................................. 8-14
9 SROM CONTROLLER ................................................................................... 9-1
9.1 Overview ................................................................................................................................................. 9-1
9.2 Features .................................................................................................................................................. 9-1
9.3 Block Diagram ......................................................................................................................................... 9-1
9.4 Functional Description ............................................................................................................................. 9-2
9.4.1 nWAIT Pin Operation ........................................................................................................................ 9-2
9.4.2 Programmable Access Cycle ........................................................................................................... 9-3
9.5 I/O Description ........................................................................................................................................ 9-4
9.6 Register Description ................................................................................................................................ 9-5
9.6.1 Register Map Summary .................................................................................................................... 9-
10 NAND FLASH CONTROLLER .................................................................. 10-1
10.1 Overview ............................................................................................................................................. 10-1
10.2 Features .............................................................................................................................................. 10-1
10.3 Functional Description ......................................................................................................................... 10-2
10.3.1 Block Diagram .............................................................................................................................. 10-2
10.3.2 NAND Flash Memory Timing ........................................................................................................ 10-3
10.4 Software Mode .................................................................................................................................... 10-4
10.4.1 Data Register Configuration ......................................................................................................... 10-4
10.4.2 1/4/8/12/16-bit ECC ...................................................................................................................... 10-5
10.4.3 2048 Byte 1-bit ECC Parity Code Assignment Table ................................................................... 10-6
10.4.4 32 Byte 1-bit ECC Parity Code Assignment Table ....................................................................... 10-6
10.4.5 1-bit ECC Module Features .......................................................................................................... 10-6
10.4.6 1-bit ECC Programming Guide ..................................................................................................... 10-7
10.4.7 4-bit ECC Programming Guide (ENCODING) .............................................................................. 10-8
10.4.8 4-bit ECC Programming Guide (DECODING) .............................................................................. 10-9
10.4.9 8/12/16-bit ECC Programming Guide (ENCODING) .................................................................. 10-10
10.4.10 8/12/16-bit ECC Programming Guide (DECODING) ................................................................ 10-11
10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC ........................................................ 10-12
10.4.12 Lock Scheme for Data Protection ............................................................................................. 10-13
10.5 Programming Constraints .................................................................................................................. 10-14
10.6 I/O Description .................................................................................................................................. 10-14
10.7 Register Description ........................................................................................................................... 10-15
10.7.1 Register Map Summary .............................................................................................................. 10-15
10.7.2 NAND Flash Interface and 1/4-bit ECC Registers ...................................................................... 10-17
10.7.3 ECC Registers for 8, 12 and 16-bit ECC .................................................................................... 10-29
11 PULSE WIDTH MODULATION TIMER ..................................................... 11-1
11.1 Overview ............................................................................................................................................. 11-1
11.2 Features .............................................................................................................................................. 11-4
11.3 PWM Operation................................................................................................................................... 11-5
11.3.1 Prescaler and Divider ................................................................................................................... 11-5
11.3.2 Basic Timer Operation .................................................................................................................. 11-6
11.3.3 Auto-Reload and Double Buffering ............................................................................................... 11-8
11.3.4 Timer Operation Example ............................................................................................................. 11-9
11.3.5 Initialize Timer (Setting Manual-Up Data and Inverter) .............................................................. 11-10
11.3.6 PWM .......................................................................................................................................... 11-10
11.3.7 During Current ISR. (Interrupt Service Routine) Output Level Control ...................................... 11-11
11.3.8 Dead Zone Generator ................................................................................................................. 11-12
11.4 I/O Description .................................................................................................................................. 11-13
11.5 Register Description ........................................................................................................................... 11-14
11.5.1 Register Map Summary .............................................................................................................. 11-14
12 WATCHDOG TIMER .................................................................................. 12-1
12.1 Overview ............................................................................................................................................. 12-1
12.2 Features .............................................................................................................................................. 12-1
12.3 Functional Description ......................................................................................................................... 12-2
12.3.1 WDT Operation ............................................................................................................................. 12-2
12.3.2 WTDAT and WTCNT .................................................................................................................... 12-3
12.3.3 WDT Start .................................................................................................................................... 12-3
12.3.4 Consideration of Debugging Environment .................................................................................... 12-3
12.4 Register Description ............................................................................................................................. 12-4
12.4.1 Register Map Summary ................................................................................................................ 12-4
13 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER ......... 13-1
13.1 Overview ............................................................................................................................................. 13-1
13.2 Features .............................................................................................................................................. 13-0
13.3 UART Description ............................................................................................................................... 13-1
13.3.1 Data Transmission ........................................................................................................................ 13-2
13.3.2 Data Reception ............................................................................................................................. 13-2
13.3.3 AFC .............................................................................................................................................. 13-3
13.3.4 Example of Non AFC (Controlling nRTS and nCTS by Software) ............................................... 13-4
13.3.5 Trigger Level of Tx/Rx FIFO and DMA Burst Size in DMA Mode ................................................ 13-4
13.3.6 RS-232C Interface ........................................................................................................................ 13-4
13.3.7 Interrupt/DMA Request Generation .............................................................................................. 13-5
13.3.8 UART Error Status FIFO .............................................................................................................. 13-7
13.4 UART Input Clock Description ........................................................................................................... 13-10
13.5 I/O Description .................................................................................................................................. 13-11
13.6 Register Description ........................................................................................................................... 13-12
13.6.1 Register Map Summary .............................................................................................................. 13-12
14 INTER-INTEGRATED CIRCUIT ................................................................. 14-1
14.1 Overview ............................................................................................................................................. 14-1
14.2 Features .............................................................................................................................................. 14-2
14.3 Functional Description ......................................................................................................................... 14-2
14.3.1 Block Diagram .............................................................................................................................. 14-2
14.4 I2C-Bus Interface Operation ................................................................................................................ 14-3
14.4.1 Start and Stop Conditions ............................................................................................................. 14-4
14.4.2 Data Transfer Format ................................................................................................................... 14-5
14.4.3 ACK Signal Transmission ............................................................................................................. 14-6
14.4.4 Read-Write Operation ................................................................................................................... 14-7
14.4.5 Bus Arbitration Procedures ........................................................................................................... 14-7
14.4.6 Abort Conditions ........................................................................................................................... 14-7
14.4.7 Configuring I2C-Bus ..................................................................................................................... 14-7
14.4.8 Flowcharts of Operations in Each Mode ...................................................................................... 14-8
14.5 I/O Description .................................................................................................................................. 14-12
14.6 Register Description ........................................................................................................................... 14-13
14.6.1 Register Map Summary .............................................................................................................. 14-13
15 SERIAL PERIPHERAL INTERFACE ......................................................... 15-1
15.1 Overview ............................................................................................................................................. 15-1
15.2 Features .............................................................................................................................................. 15-1
15.2.1 Operation of SPI ........................................................................................................................... 15-2
15.3 SPI Input Clock Description ................................................................................................................. 15-5
15.4 IO Description ..................................................................................................................................... 15-6
15.5 Register Description ............................................................................................................................. 15-7
15.5.1 Register Map Summary ................................................................................................................ 15-7
16 DISPLAY CONTROLLER .......................................................................... 16-1
16.1 Overview ............................................................................................................................................. 16-1
16.2 Features .............................................................................................................................................. 16-2
16.3 Functional Description ......................................................................................................................... 16-4
16.3.1 Brief Description ........................................................................................................................... 16-4
16.3.2 Data Flow ..................................................................................................................................... 16-5
16.3.3 Overview of the Color Data .......................................................................................................... 16-8
16.3.4 Palette Usage ............................................................................................................................. 16-23
16.3.5 Window Blending ........................................................................................................................ 16-26
16.3.6 VTIME Controller Operation ....................................................................................................... 16-35
16.3.7 Virtual Display ............................................................................................................................. 16-39
16.3.8 RGB Interface Specification ....................................................................................................... 16-40
16.3.9 LCD Indirect i80 System Interface .............................................................................................. 16-43
16.4 I/O Description .................................................................................................................................. 16-47
16.5 Register Description ........................................................................................................................... 16-48
16.5.1 Register Map Summary .............................................................................................................. 16-49
16.5.2 Palette Memory ........................................................................................................................... 16-56
16.5.3 Control Register .......................................................................................................................... 16-57
16.5.4 Gamma Lookup Table .............................................................................................................. 16-131
16.5.5 Shadow Windows Control ........................................................................................................ 16-134
16.5.6 Palette Ram .............................................................................................................................. 16-136
17 KEYPAD INTERFACE ............................................................................... 17-1
17.1 Overview ............................................................................................................................................. 17-1
17.2 Debouncing Filter ................................................................................................................................ 17-3
17.3 Filter Clock .......................................................................................................................................... 17-3
17.4 Wakeup Source................................................................................................................................... 17-3
17.5 Keypad Scanning Procedure for Software Scan ................................................................................. 17-4
17.6 Keypad Scanning Procedure for Hardware Scan ................................................................................ 17-9
17.7 I/O Description .................................................................................................................................. 17-10
17.8 Register Description ........................................................................................................................... 17-12
17.8.1 Register Map Summary .............................................................................................................. 17-12
18 ADC ........................................................................................................... 18-1
18.1 Overview ............................................................................................................................................. 18-1
18.2 Features .............................................................................................................................................. 18-1
18.3 Functional Description ......................................................................................................................... 18-1
18.3.1 Block Diagram .............................................................................................................................. 18-1
18.3.2 ADC Selection .............................................................................................................................. 18-2
18.3.3 A/D Conversion Time.................................................................................................................... 18-2
18.3.4 ADC Conversion Mode ................................................................................................................. 18-2
18.3.5 Standby Mode ............................................................................................................................... 18-3
18.4 ADC Input Clock Diagram .................................................................................................................... 18-4
18.5 I/O Descriptions................................................................................................................................... 18-5
18.6 Register Description ............................................................................................................................. 18-6
18.6.1 Register Map Summary ................................................................................................................ 18-6