Versatile Express Cortex-A5 双核核心板用户手册
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更新时间:2013/9/4 18:34:08 | 应用平台:Win9X/Win2000/WinXP |
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软件语言:英文 | 软件类别:ARM官方开发平台 > |
CoreTile Express
CoreTile Express 板在 Versatile™ Express 开发系统中提供主系统 CPU。CoreTile 必须与提供电源、配置和外设连接的主板 Express uATX 板配对使用。
处理器子板 Express 板与 Versatile 产品系列中的前代产品的不同之处在于,其内存和 LCD 控制器等高带宽外设是与 ARM 处理器一起在测试芯片中实现的。这会显示提升性能,使系统更适合进行软件基准测试并完全能运行 Debian Linux 等桌面操作系统。
处理器子板 Express 系列支持的 ARM 处理器有:
- Cortex™-A15 MPCore
- Cortex-A9 MPCore
- Cortex-A7 MPCore
- Cortex-A5 MPCore
功能列表
处理器子板名称 |
CoreTile Express |
CoreTile Express 适用于 Cortex-A9 |
CoreTile Express 适用于 Cortex-A5 |
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处理器子板名称(简称) | V2P-CA15x2_CA7x3 | V2P-CA9x4 | V2P-CA5x2s |
部件号 | V2P-CA15-0314A | V2P-CA9-0301A | V2P-CA5-0305A |
PCB 号 | HBI-0249 | HBI-0191 | HBI-0225 |
数据表 | 数据表 | 数据表 | 数据表 |
手册 | 用户手册 | 用户手册 | 用户手册 |
产品视频 | n/a | n/a | 视频 |
CPU 类型 |
Cortex-A15 MPCore™ |
Cortex-A9 MPCore | Cortex-A5 MPCore |
Cortex-A7 MPCore™ | |||
CPU 数量,速度 |
双核 CA15,1GHz 三核 CA7,800MHz |
四核,400MHz | 双核,100MHz |
CPU 版本 | r2p1,r0p1 | r0p1 | r0p1-RC0 |
协处理器 | NEON™ | NEON | NEON |
L1 高速缓存 I/D | 32KB/32KB | 32KB/32KB | 32KB/32KB |
L2 高速缓存 | 1MB | 512KB | 256KB |
TCM | N/A | N/A | N/A |
SRAM(片上) | 64KB,64 位 | 16KB,64 位 | 64KB |
SDRAM | 2GB DDR2,32 位 | 1GB DDR2,32 位 | 1GB DDR2 SODIMM |
SDRAM 速度 | 400MHz | 266MHz | 120MHz |
AMBA 总线类型 | AXI | AXI | AXI |
内部 AMBA 总线速度 | 500MHz | 200MHz | 100MHz |
外部 AMBA 总线速度 | 50MHz (M) | 50MHz (M)、30MHz (S) | 40MHz (M)、40MHz (S) |
嵌入式跟踪 | 16/32 位,PTM,ETB (4KB) | 16/32位,PTM,ETB (8KB) | ITM,ETB (8KB) |
调试连接 | JTAG 和 SWD,20 针 DIL | JTAG 和 SWD,20 针 DIL | JTAG 和 SWD,20 针 DIL |
Versatile Express Cortex-A5 双核核心板
用户手册目录
Contents
CoreTile Express A5x2 Technical Reference Manual
Preface
About this book .......................................................................................................... vii
Feedback .................................................................................................................... xi
Chapter 1 Introduction
1.1 About the CoreTile Express A5x2 daughterboard ................................................... 1-2
1.2 Precautions .............................................................................................................. 1-4
Chapter 2 Hardware Description
2.1 Overview of the CoreTile Express A5x2 daughterboard .......................................... 2-2
2.2 Cortex-A5 MPCore test chip .................................................................................... 2-4
2.3 System interconnect signals .................................................................................... 2-5
2.4 Power-up configuration and resets .......................................................................... 2-8
2.5 Clocks .................................................................................................................... 2-15
2.6 Interrupts ................................................................................................................ 2-19
2.7 Serial configuration controller ................................................................................ 2-22
2.8 Temperature monitoring ........................................................................................ 2-24
2.9 Debug .................................................................................................................... 2-25
2.10 DDR2 SO-DIMM memory interface ....................................................................... 2-27
2.11 HDLCD .................................................................................................................. 2-28
Chapter 3 Programmers Model
3.1 About this programmers model ................................................................................ 3-2
3.2 Daughterboard memory map ................................................................................... 3-3
3.3 Programmable peripherals and interfaces ............................................................... 3-7
Appendix A Signal Descriptions
A.1 Daughterboard connectors ...................................................................................... A-2
A.2 HDRX HSB multiplexing scheme ............................................................................. A-3
A.3 Header Connectors .................................................................................................. A-5
A.4 Debug and trace connectors .................................................................................... A-6
A.5 SO-DIMM connector ................................................................................................ A-9
Appendix B HDLCD controller
B.1 About the HDLCD controller .................................................................................... B-2
B.2 HDLCD programmers model ................................................................................... B-3
Appendix C Electrical Specifications
C.1 AC characteristics .................................................................................................... C-2
Appendix D Revisions